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1971 0 obj
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1972 0 obj
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1973 0 obj
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1974 0 obj
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[ (I9.1.4114) 2006 0 R (I9.1.4954) 2007 0 R (I9.1.4965) 2007 0 R (I9.1.4966) 2236 0 R (I9.1.5281) 2005 0 R (L.05XDS01INTRO) 2237 0 R (L.05XDS02MODES) 2017 0 R (L.05XDS03MEMORY) 2238 0 R (L.05XDS04PORTS) 2239 0 R (L.05XDS05CAN) 2026 0 R (L.05XDS06TIMER) 2240 0 R (L.05XDS07SCI) 2241 0 R (L.05XDS08DAC) 2242 0 R (L.05XDS09AD) 2243 0 R (L.05XDS10RESETS) 2244 0 R (L.05XDS11CPU) 2245 0 R (L.05XDS12ELEC) 2246 0 R (L.05XDS13MECH) 2247 0 R (L.05XDS14ORDER) 2248 0 R (L.05XDS15APPXA) 2249 0 R (L.05XDS16APPXB) 2031 0 R (L.05XDS17APPXC) 2250 0 R (L.05XDSBackCover) 2251 0 R (L.05XDSFrontCover) 2019 0 R (L.05XDSTitlePage) 2032 0 R (L.05XGlossary) 2252 0 R (L.05XIX) 2253 0 R (L.05XLOF) 1983 0 R (L.05XLOT) 1985 0 R (L.05XQuestB) 2254 0 R (L.05XQuestF) 2034 0 R (L.05XTOC) 1982 0 R (L.05XThumbBL) 2255 0 R (L.05XThumbBR) 2256 0 R (L.05XThumbFL) 2257 0 R (L.05XThumbFR) 2258 0 R (M10.9.10908.HeadingL3.2619.NWOI) 2259 0 R (M10.9.12750.HeadingL4.2321.Miscellaneous.register) 2260 0 R (M10.9.14313.CaptionFig.Figure.25.Slow.mode.divider.block.diagram) 2261 0 R (M10.9.14715.HeadingL3.232.IRQ.Maskable.interrupt.request) 2262 0 R (M10.9.14956.HeadingL3.217.PD0PD7) 2263 0 R (M10.9.17889.HeadingL2.142.Load.program.in.RAM.and.execute.function) 2264 0 R (M10.9.21966.HeadingL3.243.SLOW.mode) 2265 0 R (M10.9.22745.HeadingL2.143.Jump.to.any.address.function) 2266 0 R (M10.9.23904.CaptionFig.Figure.23.STOP.and.WAIT.flowcharts) 2267 0 R (M10.9.26772.CaptionFig.Figure.C3.MC68HC05B4.MC68HC05B6.jump.to.any.address.block.diagram) 2268 0 R (M10.9.27001.HeadingL2.23.LOW.POWER.MODES) 2269 0 R (M10.9.28169.CaptionFig.Figure.28) 2270 0 R (M10.9.30537.CaptionTbl.Table.21.Mode.of.operation.selection) 2271 0 R (M10.9.31377.HeadingL2.21.Modes.of.operation) 2272 0 R (M10.9.32221.CaptionFig.Figure.22.Oscillator.Connections) 2273 0 R (M10.9.33710.HeadingL2.24.Jump.to.RAM..1) 2274 0 R (M10.9.37658.CaptionFig.Figure.C2.MC68HC05B4.MC68HC05B6.load.program.in.RAM.and.execute) 2275 0 R (M10.9.40316.HeadingL1.SECTION.2) 2276 0 R (M10.9.40493.HeadingL3.211.VDD.and.VSS) 2277 0 R (M11.9.10096.HeadingL2.36.EEPROM.during.STOP.mode) 2278 0 R (M11.9.10140.TableFootnote.1.These.registers.can.only.be.accessed.when.the.reset.request.bit.in.the.c) 2279 0 R (M11.9.12750.HeadingL4.2321.Miscellaneous.register) 2280 0 R (M11.9.25219.CaptionTbl.Table.93) 2281 0 R (M11.9.25397.CaptionTbl.Table.31) 2282 0 R (M11.9.27849.HeadingL2.37.EEPROM.during.WAIT.mode) 2283 0 R (M11.9.29142.CaptionFig.Figure.32) 2284 0 R (M11.9.32378.HeadingL3.352.EEPROM.read.operation) 2285 0 R (M11.9.33068.CaptionFig.Figure.31.Memory.Map.of.the.MC68HC05L4) 2286 0 R
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endobj
1975 0 obj
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[ (M11.9.33322.CaptionTbl.Table.31.EEPROM.control.bits.description) 2172 0 R (M11.9.36428.HeadingL3.345.Options.register) 2173 0 R (M11.9.39596.HeadingL3.344.EEPROM.control.register) 2174 0 R (M12.9.11538.HeadingL2.43.Port.C) 2175 0 R (M12.9.13375.HeadingL2.42.Ports.A.B.and.C) 2176 0 R (M12.9.13540.HeadingL2.41.Inputoutput.programming) 2177 0 R (M12.9.15287.CaptionFig.Figure.43.Port.logic.levels) 2178 0 R (M12.9.21929.CaptionFig.Figure.42) 2179 0 R (M12.9.26700.CaptionTbl.Table.11.IO.Pin.States) 2180 0 R (M12.9.33820.CaptionFig.Figure.11.Standard.IO.Port.Structure) 2181 0 R (M12.9.40062.HeadingL2.45.Other.port.considerations) 2182 0 R (M13.9.12300.CaptionTbl.Table.16.Data.Length.Codes) 2183 0 R (M13.9.12643.HeadingL3.534.MCAN.interrupt.register.CINT) 2184 0 R (M13.9.13310.CaptionTbl.Table.11.Synchronisation.jump.width) 2185 0 R (M13.9.16480.HeadingL3.533.MCAN.status.register.CSTAT) 2186 0 R (M13.9.18096.CaptionTbl.Table.14.Output.control.modes) 2187 0 R (M13.9.19323.CaptionFig.Figure.16.A.typical.physical.interface.between.the.MCAN.and.the.CAN.bus.lines) 2188 0 R (M13.9.19846.HeadingL4.1334.RS..Receive.status) 2189 0 R (M13.9.19859.HeadingL2.55.Sleep.mode) 2190 0 R (M13.9.20778.HeadingL3.1310.Transmit.buffer.identifier.register.TBI) 2191 0 R (M13.9.23116.HeadingL3.1312.Transmit.data.segment.registers.TDS.1..8) 2192 0 R (M13.9.24482.HeadingL3.1311.Remote.transmission.request.and.data.length.code.register.TRTDL) 2193 0 R (M13.9.25084.CaptionFig.Figure.14.Oscillator.block.diagram) 2194 0 R (M13.9.27349.CaptionTbl.Table.12.Baud.rate.prescaler) 2195 0 R (M13.9.29142.CaptionFig.Figure.32) 2196 0 R (M13.9.30640.HeadingL4.1337.DO..Data.overrun) 2197 0 R (M13.9.30867.HeadingL1.5.motorola.CAN.MODULE.MCAN) 2198 0 R (M13.9.31576.HeadingL4.1331.BS..Bus.status) 2199 0 R (M13.9.32821.HeadingL3.532.MCAN.command.register.CCOM) 2200 0 R (M13.9.35353.CaptionTbl.Table.13.Time.segment.values) 2201 0 R (M13.9.40194.CaptionFig.Figure.52.MCAN.frame.formats) 2202 0 R (M13.9.41061.CaptionTbl.Table.15.MCAN.driver.output.levels) 2203 0 R (M13.9.41284.HeadingNoNum.Other.output.control.bits) 2204 0 R (M13.9.41993.CaptionFig.Figure.51.MCAN.block.diagram) 2205 0 R (M14.9.15013.CaptionFig.Figure.53.Timer.state.timing.diagram.for.input.capture) 2206 0 R (M14.9.18690.CaptionFig.Figure.55.Timer.state.timing.diagram.for.timer.overflow) 2207 0 R (M14.9.19792.HeadingL2.53.SOFTWARE.FORCE.COMPARE) 2208 0 R (M14.9.23813.HeadingL2.61.Counter) 2209 0 R (M14.9.26691.HeadingL3.641.Output.compare.register.1.OCR1) 2210 0 R (M14.9.26709.HeadingL2.55.Timer.during.wait.mode) 2211 0 R (M14.9.34150.HeadingL3.524.Timer.status.register.TSR) 2212 0 R (M14.9.34449.HeadingL3.631.Input.capture.register.1.ICR1) 2213 0 R (M14.9.35605.HeadingL2.55.Timer.during.stop.mode) 2214 0 R (M14.9.36490.HeadingL2.68.Timer.state.diagrams) 2215 0 R (M14.9.40756.CaptionFig.Figure.61.16bit.Programmable.Timer.Block.Diagram) 2216 0 R (M14.9.41080.CaptionFig.Figure.54.Timer.state.timing.diagram.for.output.compare) 2217 0 R (M14.9.41763.CaptionFig.Figure.52.Timer.state.timing.diagram.for.reset) 2218 0 R (M14.9.41911.HeadingL3.523.Timer.control.register.TCR) 2219 0 R (M15.9.10463.CaptionTbl.Table.64.Second.prescaler.stage.transmitter) 2220 0 R (M15.9.10701.CaptionFig.Figure.610.SCI.data.clock.timing.diagram.M1) 2221 0 R (M15.9.12283.HeadingL1.6) 2222 0 R (M15.9.13395.CaptionTbl.Table.63.First.Prescaler.Stage) 2223 0 R (M15.9.15537.CaptionFig.Figure.66.SCI.start.bit.following.a.break) 2224 0 R (M15.9.16242.HeadingL2.57.SCI.during.STOP.mode) 2225 0 R (M15.9.16955.CaptionTbl.Table.61) 2226 0 R (M15.9.19537.CaptionFig.Figure.610.SCI.rate.generator.division) 2227 0 R (M15.9.19796.HeadingL4.6828.Serial.communications.control.register.2.SCCR2) 2228 0 R (M15.9.20916.HeadingL3.683.Serial.communications.status.register.SCSR) 2229 0 R (M15.9.22627.CaptionFig.Figure.63.SCI.examples.of.start.bit.sampling.technique) 2230 0 R (M15.9.23269.CaptionTbl.Table.65.Second.prescaler.stage.receiver) 2231 0 R (M15.9.24076.HeadingL3.6115.Baud.rate.register.BAUD) 2232 0 R (M15.9.24841.HeadingL2.58.SCI.during.WAIT.mode) 2233 0 R (M15.9.27253.CaptionFig.Figure.61.Serial.communications.interface.block.diagram) 2234 0 R (M15.9.27547.CaptionTbl.Table.61.Method.of.receiver.wakeup) 2235 0 R
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endobj
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<< /First 2976 0 R /Prev 2978 0 R /Dest
[ 797 0 R /XYZ null 769 null
] /Title (12 ELECTRICAL SPECIFICATIONS) /Next 2972 0 R /Parent 2956 0 R /Last 2977 0 R /Count -6
>>
endobj
2976 0 obj
<< /Parent 2975 0 R /Dest
[ 797 0 R /XYZ null 651 null
] /Next 3176 0 R /Title (12.1 Absolute maximum ratings)
>>
endobj
2977 0 obj
<< /Parent 2975 0 R /Dest
[ 814 0 R /XYZ null 491 null
] /Prev 3173 0 R /Title (12.6 MCAN bus interface control timing characteris...)
>>
endobj
2978 0 obj
<< /First 2979 0 R /Prev 2981 0 R /Dest
[ 773 0 R /XYZ null 769 null
] /Title (11 CPU CORE AND INSTRUCTION SET) /Next 2975 0 R /Parent 2956 0 R /Last 2980 0 R /Count -3
>>
endobj
2979 0 obj
<< /First 3168 0 R /Dest
[ 773 0 R /XYZ null 649 null
] /Title (11.1 Registers) /Next 3153 0 R /Parent 2978 0 R /Last 3169 0 R /Count -5
>>
endobj
2980 0 obj
<< /First 3151 0 R /Prev 3153 0 R /Dest
[ 793 0 R /XYZ null 840 null
] /Title (11.3 Addressing modes) /Parent 2978 0 R /Last 3152 0 R /Count -10
>>
endobj
2981 0 obj
<< /First 2982 0 R /Prev 2984 0 R /Dest
[ 726 0 R /XYZ null 769 null
] /Title (10 RESETS AND INTERRUPTS) /Next 2978 0 R /Parent 2956 0 R /Last 2983 0 R /Count -2
>>
endobj
2982 0 obj
<< /First 3144 0 R /Dest
[ 726 0 R /XYZ null 685 null
] /Title (10.1 Resets) /Next 2983 0 R /Parent 2981 0 R /Last 3145 0 R /Count -5
>>
endobj
2983 0 obj
<< /First 3135 0 R /Prev 2982 0 R /Dest
[ 746 0 R /XYZ null 840 null
] /Title (10.2 Interrupts) /Parent 2981 0 R /Last 3136 0 R /Count -4
>>
endobj
2984 0 obj
<< /First 2985 0 R /Prev 2987 0 R /Dest
[ 712 0 R /XYZ null 769 null
] /Title (9 ANALOG TO DIGITAL CONVERTER) /Next 2981 0 R /Parent 2956 0 R /Last 2986 0 R /Count -5
>>
endobj
2985 0 obj
<< /Parent 2984 0 R /Dest
[ 712 0 R /XYZ null 415 null
] /Next 3131 0 R /Title (9.1 A/D converter operation)
>>
endobj
2986 0 obj
<< /Parent 2984 0 R /Dest
[ 724 0 R /XYZ null 724 null
] /Prev 3129 0 R /Title (9.5 Port D analog input)
>>
endobj
2987 0 obj
<< /First 2988 0 R /Prev 2990 0 R /Dest
[ 704 0 R /XYZ null 769 null
] /Title (8 PULSE LENGTH D/A CONVERTERS) /Next 2984 0 R /Parent 2956 0 R /Last 2989 0 R /Count -4
>>
endobj
2988 0 obj
<< /Parent 2987 0 R /Dest
[ 708 0 R /XYZ null 768 null
] /Next 3128 0 R /Title (8.1 Miscellaneous register)
>>
endobj
2989 0 obj
<< /Parent 2987 0 R /Dest
[ 710 0 R /XYZ null 531 null
] /Prev 3127 0 R /Title (8.4 PLM during WAIT mode)
>>
endobj
2990 0 obj
<< /First 2991 0 R /Prev 2993 0 R /Dest
[ 647 0 R /XYZ null 769 null
] /Title (7 SERIAL COMMUNICATIONS INTERFACE) /Next 2987 0 R /Parent 2956 0 R /Last 2992 0 R /Count -14
>>
endobj
2991 0 obj
<< /Parent 2990 0 R /Dest
[ 647 0 R /XYZ null 493 null
] /Next 3123 0 R /Title (7.1 SCI two-wire system features)
>>
endobj
2992 0 obj
<< /Parent 2990 0 R /Dest
[ 700 0 R /XYZ null 402 null
] /Prev 3108 0 R /Title (7.14 SCI during WAIT mode)
>>
endobj
2993 0 obj
<< /First 2994 0 R /Prev 2996 0 R /Dest
[ 622 0 R /XYZ null 769 null
] /Title (6 PROGRAMMABLE TIMER) /Next 2990 0 R /Parent 2956 0 R /Last 2995 0 R /Count -8
>>
endobj
2994 0 obj
<< /First 3107 0 R /Dest
[ 622 0 R /XYZ null 403 null
] /Title (6.1 Counter) /Next 3103 0 R /Parent 2993 0 R /Last 3107 0 R /Count -1
>>
endobj
2995 0 obj
<< /Parent 2993 0 R /Dest
[ 644 0 R /XYZ null 572 null
] /Prev 3093 0 R /Title (6.8 Timer state diagrams)
>>
endobj
2996 0 obj
<< /First 2997 0 R /Prev 2999 0 R /Dest
[ 571 0 R /XYZ null 769 null
] /Title (5 MOTOROLA CAN MODULE \(MCAN\)) /Next 2993 0 R /Parent 2956 0 R /Last 2998 0 R /Count -5
>>
endobj
2997 0 obj
<< /Parent 2996 0 R /Dest
[ 576 0 R /XYZ null 840 null
] /Next 3079 0 R /Title (5.1 TBF Transmit buffer)
>>
endobj
2998 0 obj
<< /First 3073 0 R /Prev 3074 0 R /Dest
[ 616 0 R /XYZ null 513 null
] /Title (5.5 Sleep mode) /Parent 2996 0 R /Last 3073 0 R /Count -1
>>
endobj
2999 0 obj
<< /First 3000 0 R /Prev 3002 0 R /Dest
[ 557 0 R /XYZ null 769 null
] /Title (4 INPUT/OUTPUT PORTS) /Next 2996 0 R /Parent 2956 0 R /Last 3001 0 R /Count -6
>>
endobj
3000 0 obj
<< /Parent 2999 0 R /Dest
[ 557 0 R /XYZ null 601 null
] /Next 3069 0 R /Title (4.1 Input/output programming)
>>
endobj
3001 0 obj
<< /Parent 2999 0 R /Dest
[ 567 0 R /XYZ null 657 null
] /Prev 3064 0 R /Title (4.6 Other port considerations)
>>
endobj
3002 0 obj
<< /First 3003 0 R /Prev 3005 0 R /Dest
[ 522 0 R /XYZ null 769 null
] /Title (3 MEMORY AND REGISTERS) /Next 2999 0 R /Parent 2956 0 R /Last 3004 0 R /Count -8
>>
endobj
3003 0 obj
<< /Parent 3002 0 R /Dest
[ 522 0 R /XYZ null 637 null
] /Next 3060 0 R /Title (3.1 Registers)
>>
endobj
3004 0 obj
<< /Parent 3002 0 R /Dest
[ 547 0 R /XYZ null 840 null
] /Prev 3053 0 R /Title (3.8 Miscellaneous register)
>>
endobj
3005 0 obj
<< /First 3006 0 R /Prev 3008 0 R /Dest
[ 454 0 R /XYZ null 769 null
] /Title (2 MODES OF OPERATION AND PIN DESCRIPTIONS) /Next 3002 0 R /Parent 2956 0 R /Last 3007 0 R /Count -3
>>
endobj
3006 0 obj
<< /First 3048 0 R /Dest
[ 454 0 R /XYZ null 661 null
] /Title (2.1 Modes of operation) /Next 3015 0 R /Parent 3005 0 R /Last 3049 0 R /Count -2
>>
endobj
3007 0 obj
<< /First 3013 0 R /Prev 3015 0 R /Dest
[ 494 0 R /XYZ null 840 null
] /Title (2.3 Pin descriptions) /Parent 3005 0 R /Last 3014 0 R /Count -25
>>
endobj
3008 0 obj
<< /First 3009 0 R /Prev 3011 0 R /Dest
[ 447 0 R /XYZ null 769 null
] /Title (1 INTRODUCTION) /Next 3005 0 R /Parent 2956 0 R /Last 3010 0 R /Count -2
>>
endobj
3009 0 obj
<< /Parent 3008 0 R /Dest
[ 451 0 R /XYZ null 840 null
] /Next 3010 0 R /Title (1.1 Features)
>>
endobj
3010 0 obj
<< /Parent 3008 0 R /Dest
[ 452 0 R /XYZ null 840 null
] /Prev 3009 0 R /Title (1.2 Mask options for the MC68HC05X16)
>>
endobj
3011 0 obj
<< /Prev 3012 0 R /Dest
[ 379 0 R /XYZ null 769 null
] /Title (LIST OF TABLES) /Next 3008 0 R /Parent 2956 0 R
>>
endobj
3012 0 obj
<< /Prev 2957 0 R /Dest
[ 316 0 R /XYZ null 769 null
] /Title (LIST OF FIGURES) /Next 3011 0 R /Parent 2956 0 R
>>
endobj
3013 0 obj
<< /Parent 3007 0 R /Dest
[ 494 0 R /XYZ null 802 null
] /Next 3045 0 R /Title (2.3.1 VDD and VSS)
>>
endobj
3014 0 obj
<< /Parent 3007 0 R /Dest
[ 520 0 R /XYZ null 572 null
] /Prev 3021 0 R /Title (2.3.25 TX0/TX1)
>>
endobj
3015 0 obj
<< /First 3016 0 R /Prev 3006 0 R /Dest
[ 467 0 R /XYZ null 840 null
] /Title (2.2 Low power modes) /Next 3007 0 R /Parent 3005 0 R /Last 3017 0 R /Count -3
>>
endobj
3016 0 obj
<< /Parent 3015 0 R /Dest
[ 467 0 R /XYZ null 753 null
] /Next 3019 0 R /Title (2.2.1 STOP mode)
>>
endobj
3017 0 obj
<< /First 3018 0 R /Prev 3019 0 R /Dest
[ 482 0 R /XYZ null 540 null
] /Title (2.2.3 SLOW mode) /Parent 3015 0 R /Last 3018 0 R /Count -1
>>
endobj
3018 0 obj
<< /Parent 3017 0 R /Dest
[ 492 0 R /XYZ null 617 null
] /Title (2.2.3.1 Miscellaneous register)
>>
endobj
3019 0 obj
<< /First 3020 0 R /Prev 3016 0 R /Dest
[ 479 0 R /XYZ null 840 null
] /Title (2.2.2 WAIT mode) /Next 3017 0 R /Parent 3015 0 R /Last 3020 0 R /Count -1
>>
endobj
3020 0 obj
<< /Parent 3019 0 R /Dest
[ 482 0 R /XYZ null 681 null
] /Title (2.2.2.1 Power consumption during WAIT mode)
>>
endobj
3021 0 obj
<< /Prev 3022 0 R /Dest
[ 520 0 R /XYZ null 645 null
] /Title (2.3.24 RX0/RX1) /Next 3014 0 R /Parent 3007 0 R
>>
endobj
3022 0 obj
<< /Prev 3023 0 R /Dest
[ 520 0 R /XYZ null 718 null
] /Title (2.3.23 VDDH) /Next 3021 0 R /Parent 3007 0 R
>>
endobj
3023 0 obj
<< /Prev 3024 0 R /Dest
[ 520 0 R /XYZ null 779 null
] /Title (2.3.22 VSS1) /Next 3022 0 R /Parent 3007 0 R
>>
endobj
3024 0 obj
<< /Prev 3025 0 R /Dest
[ 520 0 R /XYZ null 840 null
] /Title (2.3.21 VDD1) /Next 3023 0 R /Parent 3007 0 R
>>
endobj
3025 0 obj
<< /Prev 3026 0 R /Dest
[ 513 0 R /XYZ null 396 null
] /Title (2.3.20 PD0/AN0PD7/AN7) /Next 3024 0 R /Parent 3007 0 R
>>
endobj
3026 0 obj
<< /Prev 3027 0 R /Dest
[ 513 0 R /XYZ null 517 null
] /Title (2.3.19 NWOI) /Next 3025 0 R /Parent 3007 0 R
>>
endobj
3027 0 obj
<< /Prev 3028 0 R /Dest
[ 513 0 R /XYZ null 651 null
] /Title (2.3.18 PA0 PA7/PB0 PB7/PC0 PC7) /Next 3026 0 R /Parent 3007 0 R
>>
endobj
3028 0 obj
<< /Prev 3029 0 R /Dest
[ 513 0 R /XYZ null 714 null
] /Title (2.3.17 VRL) /Next 3027 0 R /Parent 3007 0 R
>>
endobj
3029 0 obj
<< /Prev 3030 0 R /Dest
[ 513 0 R /XYZ null 777 null
] /Title (2.3.16 VRH) /Next 3028 0 R /Parent 3007 0 R
>>
endobj
3030 0 obj
<< /Prev 3031 0 R /Dest
[ 513 0 R /XYZ null 840 null
] /Title (2.3.15 VPP1) /Next 3029 0 R /Parent 3007 0 R
>>
endobj
3031 0 obj
<< /Prev 3032 0 R /Dest
[ 510 0 R /XYZ null 342 null
] /Title (2.3.14 PLMB) /Next 3030 0 R /Parent 3007 0 R
>>
endobj
3032 0 obj
<< /Prev 3033 0 R /Dest
[ 510 0 R /XYZ null 405 null
] /Title (2.3.13 PLMA) /Next 3031 0 R /Parent 3007 0 R
>>
endobj
3033 0 obj
<< /First 3034 0 R /Prev 3036 0 R /Dest
[ 501 0 R /XYZ null 777 null
] /Title (2.3.12 OSC1, OSC2) /Next 3032 0 R /Parent 3007 0 R /Last 3035 0 R /Count -4
>>
endobj
3034 0 obj
<< /Parent 3033 0 R /Dest
[ 501 0 R /XYZ null 672 null
] /Next 3047 0 R /Title (2.3.12.1 Crystal)
>>
endobj
3035 0 obj
<< /Parent 3033 0 R /Dest
[ 510 0 R /XYZ null 840 null
] /Prev 3046 0 R /Title (2.3.12.4 Oscillator division)
>>
endobj
3036 0 obj
<< /Prev 3037 0 R /Dest
[ 501 0 R /XYZ null 840 null
] /Title (2.3.11 SCLK) /Next 3033 0 R /Parent 3007 0 R
>>
endobj
3037 0 obj
<< /Prev 3038 0 R /Dest
[ 499 0 R /XYZ null 372 null
] /Title (2.3.10 TDO \(Transmit data out\)) /Next 3036 0 R /Parent 3007 0 R
>>
endobj
3038 0 obj
<< /Prev 3039 0 R /Dest
[ 499 0 R /XYZ null 435 null
] /Title (2.3.9 RDI \(Receive data in\)) /Next 3037 0 R /Parent 3007 0 R
>>
endobj
3039 0 obj
<< /Prev 3040 0 R /Dest
[ 499 0 R /XYZ null 498 null
] /Title (2.3.8 TCMP2) /Next 3038 0 R /Parent 3007 0 R
>>
endobj
3040 0 obj
<< /Prev 3041 0 R /Dest
[ 499 0 R /XYZ null 561 null
] /Title (2.3.7 TCMP1) /Next 3039 0 R /Parent 3007 0 R
>>
endobj
3041 0 obj
<< /Prev 3042 0 R /Dest
[ 499 0 R /XYZ null 624 null
] /Title (2.3.6 TCAP2) /Next 3040 0 R /Parent 3007 0 R
>>
endobj
3042 0 obj
<< /Prev 3043 0 R /Dest
[ 499 0 R /XYZ null 687 null
] /Title (2.3.5 TCAP1) /Next 3041 0 R /Parent 3007 0 R
>>
endobj
3043 0 obj
<< /Prev 3044 0 R /Dest
[ 499 0 R /XYZ null 840 null
] /Title (2.3.4 MDS) /Next 3042 0 R /Parent 3007 0 R
>>
endobj
3044 0 obj
<< /Prev 3045 0 R /Dest
[ 494 0 R /XYZ null 472 null
] /Title (2.3.3 RESET) /Next 3043 0 R /Parent 3007 0 R
>>
endobj
3045 0 obj
<< /Prev 3013 0 R /Dest
[ 494 0 R /XYZ null 649 null
] /Title (2.3.2 IRQ) /Next 3044 0 R /Parent 3007 0 R
>>
endobj
3046 0 obj
<< /Prev 3047 0 R /Dest
[ 501 0 R /XYZ null 390 null
] /Title (2.3.12.3 External clock) /Next 3035 0 R /Parent 3033 0 R
>>
endobj
3047 0 obj
<< /Prev 3034 0 R /Dest
[ 501 0 R /XYZ null 519 null
] /Title (2.3.12.2 Ceramic resonator) /Next 3046 0 R /Parent 3033 0 R
>>
endobj
3048 0 obj
<< /Parent 3006 0 R /Dest
[ 454 0 R /XYZ null 386 null
] /Next 3049 0 R /Title (2.1.1 Single-chip mode)
>>
endobj
3049 0 obj
<< /First 3050 0 R /Prev 3048 0 R /Dest
[ 456 0 R /XYZ null 840 null
] /Title (2.1.2 Bootstrap mode) /Parent 3006 0 R /Last 3051 0 R /Count -3
>>
endobj
3050 0 obj
<< /Parent 3049 0 R /Dest
[ 458 0 R /XYZ null 798 null
] /Next 3052 0 R /Title (2.1.2.1 Serial RAM loader)
>>
endobj
3051 0 obj
<< /Parent 3049 0 R /Dest
[ 458 0 R /XYZ null 408 null
] /Prev 3052 0 R /Title (2.1.2.3 Jump to any address)
>>
endobj
3052 0 obj
<< /Prev 3050 0 R /Dest
[ 458 0 R /XYZ null 501 null
] /Title (2.1.2.2 Jump to RAM + 1) /Next 3051 0 R /Parent 3049 0 R
>>
endobj
3053 0 obj
<< /Prev 3054 0 R /Dest
[ 539 0 R /XYZ null 472 null
] /Title (3.7 EEPROM during WAIT mode) /Next 3004 0 R /Parent 3002 0 R
>>
endobj
3054 0 obj
<< /Prev 3055 0 R /Dest
[ 539 0 R /XYZ null 558 null
] /Title (3.6 EEPROM during STOP mode) /Next 3053 0 R /Parent 3002 0 R
>>
endobj
3055 0 obj
<< /First 3056 0 R /Prev 3058 0 R /Dest
[ 527 0 R /XYZ null 840 null
] /Title (3.5 EEPROM) /Next 3054 0 R /Parent 3002 0 R /Last 3057 0 R /Count -5
>>
endobj
3056 0 obj
<< /Parent 3055 0 R /Dest
[ 527 0 R /XYZ null 526 null
] /Next 3063 0 R /Title (3.5.1 EEPROM control register)
>>
endobj
3057 0 obj
<< /Parent 3055 0 R /Dest
[ 537 0 R /XYZ null 433 null
] /Prev 3061 0 R /Title (3.5.5 Options register \(OPTR\))
>>
endobj
3058 0 obj
<< /Prev 3059 0 R /Dest
[ 526 0 R /XYZ null 430 null
] /Title (3.4 Bootstrap ROM) /Next 3055 0 R /Parent 3002 0 R
>>
endobj
3059 0 obj
<< /Prev 3060 0 R /Dest
[ 522 0 R /XYZ null 371 null
] /Title (3.3 ROM) /Next 3058 0 R /Parent 3002 0 R
>>
endobj
3060 0 obj
<< /Prev 3003 0 R /Dest
[ 522 0 R /XYZ null 508 null
] /Title (3.2 RAM) /Next 3059 0 R /Parent 3002 0 R
>>
endobj
3061 0 obj
<< /Prev 3062 0 R /Dest
[ 537 0 R /XYZ null 750 null
] /Title (3.5.4 EEPROM programming operation) /Next 3057 0 R /Parent 3055 0 R
>>
endobj
3062 0 obj
<< /Prev 3063 0 R /Dest
[ 535 0 R /XYZ null 546 null
] /Title (3.5.3 EEPROM erase operation) /Next 3061 0 R /Parent 3055 0 R
>>
endobj
3063 0 obj
<< /Prev 3056 0 R /Dest
[ 535 0 R /XYZ null 717 null
] /Title (3.5.2 EEPROM read operation) /Next 3062 0 R /Parent 3055 0 R
>>
endobj
3064 0 obj
<< /First 3065 0 R /Prev 3067 0 R /Dest
[ 564 0 R /XYZ null 634 null
] /Title (4.5 Port registers) /Next 3001 0 R /Parent 2999 0 R /Last 3066 0 R /Count -5
>>
endobj
3065 0 obj
<< /Parent 3064 0 R /Dest
[ 564 0 R /XYZ null 560 null
] /Next 3072 0 R /Title (4.5.1 Port data registers A and B \(PORTA and PORTB...)
>>
endobj
3066 0 obj
<< /Parent 3064 0 R /Dest
[ 567 0 R /XYZ null 840 null
] /Prev 3070 0 R /Title (4.5.5 Data direction registers \(DDRA, DDRB and DDR...)
>>
endobj
3067 0 obj
<< /Prev 3068 0 R /Dest
[ 564 0 R /XYZ null 840 null
] /Title (4.4 Port D) /Next 3064 0 R /Parent 2999 0 R
>>
endobj
3068 0 obj
<< /Prev 3069 0 R /Dest
[ 562 0 R /XYZ null 780 null
] /Title (4.3 Port C) /Next 3067 0 R /Parent 2999 0 R
>>
endobj
3069 0 obj
<< /Prev 3000 0 R /Dest
[ 559 0 R /XYZ null 438 null
] /Title (4.2 Ports A and B) /Next 3068 0 R /Parent 2999 0 R
>>
endobj
3070 0 obj
<< /Prev 3071 0 R /Dest
[ 565 0 R /XYZ null 517 null
] /Title (4.5.4 A/D status/control register) /Next 3066 0 R /Parent 3064 0 R
>>
endobj
3071 0 obj
<< /Prev 3072 0 R /Dest
[ 565 0 R /XYZ null 658 null
] /Title (4.5.3 Port data register D \(PORTD\)) /Next 3070 0 R /Parent 3064 0 R
>>
endobj
3072 0 obj
<< /Prev 3065 0 R /Dest
[ 565 0 R /XYZ null 840 null
] /Title (4.5.2 Port data register C \(PORTC\)) /Next 3071 0 R /Parent 3064 0 R
>>
endobj
3073 0 obj
<< /Parent 2998 0 R /Dest
[ 618 0 R /XYZ null 750 null
] /Title (5.5.1 Sleep comparator reference)
>>
endobj
3074 0 obj
<< /First 3075 0 R /Prev 3076 0 R /Dest
[ 610 0 R /XYZ null 537 null
] /Title (5.4 Interface to the MCAN bus) /Next 2998 0 R /Parent 2996 0 R /Last 3075 0 R /Count -1
>>
endobj
3075 0 obj
<< /Parent 3074 0 R /Dest
[ 616 0 R /XYZ null 714 null
] /Title (5.4.1 Single wire operation)
>>
endobj
3076 0 obj
<< /First 3077 0 R /Prev 3079 0 R /Dest
[ 576 0 R /XYZ null 426 null
] /Title (5.3 Interface to the MC68HC05X16 CPU) /Next 3074 0 R /Parent 2996 0 R /Last 3078 0 R /Count -15
>>
endobj
3077 0 obj
<< /Parent 3076 0 R /Dest
[ 579 0 R /XYZ null 840 null
] /Next 3092 0 R /Title (5.3.1 MCAN control register \(CCNTRL\))
>>
endobj
3078 0 obj
<< /Parent 3076 0 R /Dest
[ 610 0 R /XYZ null 710 null
] /Prev 3080 0 R /Title (5.3.15 Receive data segment registers \(RDS\) 1 8)
>>
endobj
3079 0 obj
<< /Prev 2997 0 R /Dest
[ 576 0 R /XYZ null 663 null
] /Title (5.2 RBF Receive buffer) /Next 3076 0 R /Parent 2996 0 R
>>
endobj
3080 0 obj
<< /Prev 3081 0 R /Dest
[ 610 0 R /XYZ null 840 null
] /Title (5.3.14 Remote transmission request and data length...) /Next 3078 0 R /Parent 3076 0 R
>>
endobj
3081 0 obj
<< /Prev 3082 0 R /Dest
[ 608 0 R /XYZ null 502 null
] /Title (5.3.13 Receive buffer identifier register \(RBI\)) /Next 3080 0 R /Parent 3076 0 R
>>
endobj
3082 0 obj
<< /Prev 3083 0 R /Dest
[ 608 0 R /XYZ null 657 null
] /Title (5.3.12 Transmit data segment registers \(TDS\) 1 8...) /Next 3081 0 R /Parent 3076 0 R
>>
endobj
3083 0 obj
<< /Prev 3084 0 R /Dest
[ 606 0 R /XYZ null 671 null
] /Title (5.3.11 Remote transmission request and data length...) /Next 3082 0 R /Parent 3076 0 R
>>
endobj
3084 0 obj
<< /Prev 3085 0 R /Dest
[ 606 0 R /XYZ null 840 null
] /Title (5.3.10 Transmit buffer identifier register \(TBI\)...) /Next 3083 0 R /Parent 3076 0 R
>>
endobj
3085 0 obj
<< /Prev 3086 0 R /Dest
[ 601 0 R /XYZ null 840 null
] /Title (5.3.9 MCAN output control register \(COCNTRL\)) /Next 3084 0 R /Parent 3076 0 R
>>
endobj
3086 0 obj
<< /Prev 3087 0 R /Dest
[ 598 0 R /XYZ null 840 null
] /Title (5.3.8 MCAN bus timing register 1 \(CBT1\)) /Next 3085 0 R /Parent 3076 0 R
>>
endobj
3087 0 obj
<< /Prev 3088 0 R /Dest
[ 593 0 R /XYZ null 533 null
] /Title (5.3.7 MCAN bus timing register 0 \(CBT0\)) /Next 3086 0 R /Parent 3076 0 R
>>
endobj
3088 0 obj
<< /Prev 3089 0 R /Dest
[ 593 0 R /XYZ null 840 null
] /Title (5.3.6 MCAN acceptance mask register \(CACM\)) /Next 3087 0 R /Parent 3076 0 R
>>
endobj
3089 0 obj
<< /Prev 3090 0 R /Dest
[ 592 0 R /XYZ null 726 null
] /Title (5.3.5 MCAN acceptance code register \(CACC\)) /Next 3088 0 R /Parent 3076 0 R
>>
endobj
3090 0 obj
<< /Prev 3091 0 R /Dest
[ 591 0 R /XYZ null 840 null
] /Title (5.3.4 MCAN interrupt register \(CINT\)) /Next 3089 0 R /Parent 3076 0 R
>>
endobj
3091 0 obj
<< /Prev 3092 0 R /Dest
[ 589 0 R /XYZ null 840 null
] /Title (5.3.3 MCAN status register \(CSTAT\)) /Next 3090 0 R /Parent 3076 0 R
>>
endobj
3092 0 obj
<< /Prev 3077 0 R /Dest
[ 580 0 R /XYZ null 456 null
] /Title (5.3.2 MCAN command register \(CCOM\)) /Next 3091 0 R /Parent 3076 0 R
>>
endobj
3093 0 obj
<< /Prev 3094 0 R /Dest
[ 644 0 R /XYZ null 646 null
] /Title (6.7 Timer during WAIT mode) /Next 2995 0 R /Parent 2993 0 R
>>
endobj
3094 0 obj
<< /Prev 3095 0 R /Dest
[ 644 0 R /XYZ null 840 null
] /Title (6.6 Timer during STOP mode) /Next 3093 0 R /Parent 2993 0 R
>>
endobj
3095 0 obj
<< /First 3096 0 R /Prev 3097 0 R /Dest
[ 642 0 R /XYZ null 549 null
] /Title (6.5 Pulse length modulation \(PLM\)) /Next 3094 0 R /Parent 2993 0 R /Last 3096 0 R /Count -1
>>
endobj
3096 0 obj
<< /Parent 3095 0 R /Dest
[ 642 0 R /XYZ null 481 null
] /Title (6.5.1 Pulse length modulation registers A and B \(P...)
>>
endobj
3097 0 obj
<< /First 3098 0 R /Prev 3100 0 R /Dest
[ 640 0 R /XYZ null 840 null
] /Title (6.4 Output compare) /Next 3095 0 R /Parent 2993 0 R /Last 3099 0 R /Count -3
>>
endobj
3098 0 obj
<< /Parent 3097 0 R /Dest
[ 640 0 R /XYZ null 682 null
] /Next 3106 0 R /Title (6.4.1 Output compare register 1 \(OCR1\))
>>
endobj
3099 0 obj
<< /Parent 3097 0 R /Dest
[ 642 0 R /XYZ null 750 null
] /Prev 3106 0 R /Title (6.4.3 Software force compare)
>>
endobj
3100 0 obj
<< /First 3101 0 R /Prev 3103 0 R /Dest
[ 636 0 R /XYZ null 612 null
] /Title (6.3 Input capture) /Next 3097 0 R /Parent 2993 0 R /Last 3102 0 R /Count -2
>>
endobj
3101 0 obj
<< /Parent 3100 0 R /Dest
[ 636 0 R /XYZ null 490 null
] /Next 3102 0 R /Title (6.3.1 Input capture register 1 \(ICR1\))
>>
endobj
3102 0 obj
<< /Parent 3100 0 R /Dest
[ 637 0 R /XYZ null 642 null
] /Prev 3101 0 R /Title (6.3.2 Input capture register 2 \(ICR2\))
>>
endobj
3103 0 obj
<< /First 3104 0 R /Prev 2994 0 R /Dest
[ 631 0 R /XYZ null 840 null
] /Title (6.2 Timer control and status) /Next 3100 0 R /Parent 2993 0 R /Last 3105 0 R /Count -2
>>
endobj
3104 0 obj
<< /Parent 3103 0 R /Dest
[ 631 0 R /XYZ null 766 null
] /Next 3105 0 R /Title (6.2.1 Timer control register \(TCR\))
>>
endobj
3105 0 obj
<< /Parent 3103 0 R /Dest
[ 635 0 R /XYZ null 840 null
] /Prev 3104 0 R /Title (6.2.2 Timer status register \(TSR\))
>>
endobj
3106 0 obj
<< /Prev 3098 0 R /Dest
[ 641 0 R /XYZ null 750 null
] /Title (6.4.2 Output compare register 2 \(OCR2\)) /Next 3099 0 R /Parent 3097 0 R
>>
endobj
3107 0 obj
<< /Parent 2994 0 R /Dest
[ 629 0 R /XYZ null 840 null
] /Title (6.1.1 Counter register and alternate counter regis...)
>>
endobj
3108 0 obj
<< /Prev 3109 0 R /Dest
[ 700 0 R /XYZ null 591 null
] /Title (7.13 SCI during STOP mode) /Next 2992 0 R /Parent 2990 0 R
>>
endobj
3109 0 obj
<< /Prev 3110 0 R /Dest
[ 698 0 R /XYZ null 840 null
] /Title (7.12 Baud rate selection) /Next 3108 0 R /Parent 2990 0 R
>>
endobj
3110 0 obj
<< /First 3111 0 R /Prev 3113 0 R /Dest
[ 675 0 R /XYZ null 840 null
] /Title (7.11 SCI registers) /Next 3109 0 R /Parent 2990 0 R /Last 3112 0 R /Count -5
>>
endobj
3111 0 obj
<< /Parent 3110 0 R /Dest
[ 675 0 R /XYZ null 766 null
] /Next 3126 0 R /Title (7.11.1 Serial communications data register \(SCDR\)...)
>>
endobj
3112 0 obj
<< /Parent 3110 0 R /Dest
[ 694 0 R /XYZ null 840 null
] /Prev 3124 0 R /Title (7.11.5 Baud rate register \(BAUD\))
>>
endobj
3113 0 obj
<< /Prev 3114 0 R /Dest
[ 671 0 R /XYZ null 840 null
] /Title (7.10 SCI synchronous transmission) /Next 3110 0 R /Parent 2990 0 R
>>
endobj
3114 0 obj
<< /Prev 3115 0 R /Dest
[ 667 0 R /XYZ null 398 null
] /Title (7.9 Transmit data out \(TDO\)) /Next 3113 0 R /Parent 2990 0 R
>>
endobj
3115 0 obj
<< /Prev 3116 0 R /Dest
[ 657 0 R /XYZ null 412 null
] /Title (7.8 Start bit detection) /Next 3114 0 R /Parent 2990 0 R
>>
endobj
3116 0 obj
<< /Prev 3117 0 R /Dest
[ 657 0 R /XYZ null 606 null
] /Title (7.7 Receive data in \(RDI\)) /Next 3115 0 R /Parent 2990 0 R
>>
endobj
3117 0 obj
<< /First 3118 0 R /Prev 3120 0 R /Dest
[ 655 0 R /XYZ null 513 null
] /Title (7.6 Receiver wake-up operation) /Next 3116 0 R /Parent 2990 0 R /Last 3119 0 R /Count -2
>>
endobj
3118 0 obj
<< /Parent 3117 0 R /Dest
[ 657 0 R /XYZ null 840 null
] /Next 3119 0 R /Title (7.6.1 Idle line wake-up)
>>
endobj
3119 0 obj
<< /Parent 3117 0 R /Dest
[ 657 0 R /XYZ null 741 null
] /Prev 3118 0 R /Title (7.6.2 Address mark wake-up)
>>
endobj
3120 0 obj
<< /Prev 3121 0 R /Dest
[ 655 0 R /XYZ null 840 null
] /Title (7.5 Data format) /Next 3117 0 R /Parent 2990 0 R
>>
endobj
3121 0 obj
<< /Prev 3122 0 R /Dest
[ 649 0 R /XYZ null 566 null
] /Title (7.4 Functional description) /Next 3120 0 R /Parent 2990 0 R
>>
endobj
3122 0 obj
<< /Prev 3123 0 R /Dest
[ 649 0 R /XYZ null 676 null
] /Title (7.3 SCI transmitter features) /Next 3121 0 R /Parent 2990 0 R
>>
endobj
3123 0 obj
<< /Prev 2991 0 R /Dest
[ 649 0 R /XYZ null 840 null
] /Title (7.2 SCI receiver features) /Next 3122 0 R /Parent 2990 0 R
>>
endobj
3124 0 obj
<< /Prev 3125 0 R /Dest
[ 691 0 R /XYZ null 840 null
] /Title (7.11.4 Serial communications status register \(SCSR...) /Next 3112 0 R /Parent 3110 0 R
>>
endobj
3125 0 obj
<< /Prev 3126 0 R /Dest
[ 689 0 R /XYZ null 840 null
] /Title (7.11.3 Serial communications control register 2 \(S...) /Next 3124 0 R /Parent 3110 0 R
>>
endobj
3126 0 obj
<< /Prev 3111 0 R /Dest
[ 675 0 R /XYZ null 455 null
] /Title (7.11.2 Serial communications control register 1 \(S...) /Next 3125 0 R /Parent 3110 0 R
>>
endobj
3127 0 obj
<< /Prev 3128 0 R /Dest
[ 710 0 R /XYZ null 617 null
] /Title (8.3 PLM during STOP mode) /Next 2989 0 R /Parent 2987 0 R
>>
endobj
3128 0 obj
<< /Prev 2988 0 R /Dest
[ 710 0 R /XYZ null 840 null
] /Title (8.2 PLM clock selection) /Next 3127 0 R /Parent 2987 0 R
>>
endobj
3129 0 obj
<< /Prev 3130 0 R /Dest
[ 724 0 R /XYZ null 840 null
] /Title (9.4 A/D converter during WAIT mode) /Next 2986 0 R /Parent 2984 0 R
>>
endobj
3130 0 obj
<< /Prev 3131 0 R /Dest
[ 721 0 R /XYZ null 363 null
] /Title (9.3 A/D converter during STOP mode) /Next 3129 0 R /Parent 2984 0 R
>>
endobj
3131 0 obj
<< /First 3132 0 R /Prev 2985 0 R /Dest
[ 717 0 R /XYZ null 840 null
] /Title (9.2 A/D registers) /Next 3130 0 R /Parent 2984 0 R /Last 3133 0 R /Count -3
>>
endobj
3132 0 obj
<< /Parent 3131 0 R /Dest
[ 717 0 R /XYZ null 802 null
] /Next 3134 0 R /Title (9.2.1 Port D data register \(PORTD\))
>>
endobj
3133 0 obj
<< /Parent 3131 0 R /Dest
[ 718 0 R /XYZ null 840 null
] /Prev 3134 0 R /Title (9.2.3 A/D status/control register \(ADSTAT\))
>>
endobj
3134 0 obj
<< /Prev 3132 0 R /Dest
[ 717 0 R /XYZ null 565 null
] /Title (9.2.2 A/D result data register \(ADDATA\)) /Next 3133 0 R /Parent 3131 0 R
>>
endobj
3135 0 obj
<< /Parent 2983 0 R /Dest
[ 749 0 R /XYZ null 840 null
] /Next 3140 0 R /Title (10.2.1 Interrupt priorities)
>>
endobj
3136 0 obj
<< /Parent 2983 0 R /Dest
[ 770 0 R /XYZ null 840 null
] /Prev 3137 0 R /Title (10.2.4 Hardware controlled interrupt sequence)
>>
endobj
3137 0 obj
<< /First 3138 0 R /Prev 3140 0 R /Dest
[ 749 0 R /XYZ null 411 null
] /Title (10.2.3 Maskable hardware interrupts) /Next 3136 0 R /Parent 2983 0 R /Last 3139 0 R /Count -5
>>
endobj
3138 0 obj
<< /Parent 3137 0 R /Dest
[ 752 0 R /XYZ null 840 null
] /Next 3143 0 R /Title (10.2.3.1 Miscellaneous register)
>>
endobj
3139 0 obj
<< /Parent 3137 0 R /Dest
[ 762 0 R /XYZ null 549 null
] /Prev 3141 0 R /Title (10.2.3.5 Serial communications interface \(SCI\) int...)
>>
endobj
3140 0 obj
<< /Prev 3135 0 R /Dest
[ 749 0 R /XYZ null 522 null
] /Title (10.2.2 Nonmaskable software interrupt \(SWI\)) /Next 3137 0 R /Parent 2983 0 R
>>
endobj
3141 0 obj
<< /Prev 3142 0 R /Dest
[ 762 0 R /XYZ null 708 null
] /Title (10.2.3.4 Timer interrupts) /Next 3139 0 R /Parent 3137 0 R
>>
endobj
3142 0 obj
<< /Prev 3143 0 R /Dest
[ 756 0 R /XYZ null 435 null
] /Title (10.2.3.3 MCAN interrupt \(CIRQ\)) /Next 3141 0 R /Parent 3137 0 R
>>
endobj
3143 0 obj
<< /Prev 3138 0 R /Dest
[ 756 0 R /XYZ null 750 null
] /Title (10.2.3.2 External interrupts) /Next 3142 0 R /Parent 3137 0 R
>>
endobj
3144 0 obj
<< /Parent 2982 0 R /Dest
[ 729 0 R /XYZ null 840 null
] /Next 3150 0 R /Title (10.1.1 Power-on reset)
>>
endobj
3145 0 obj
<< /Parent 2982 0 R /Dest
[ 739 0 R /XYZ null 608 null
] /Prev 3146 0 R /Title (10.1.5 Functions affected by reset)
>>
endobj
3146 0 obj
<< /First 3147 0 R /Prev 3149 0 R /Dest
[ 733 0 R /XYZ null 488 null
] /Title (10.1.4 Computer operating properly \(COP\) watchdog ...) /Next 3145 0 R /Parent 2982 0 R /Last 3148 0 R /Count -2
>>
endobj
3147 0 obj
<< /Parent 3146 0 R /Dest
[ 739 0 R /XYZ null 840 null
] /Next 3148 0 R /Title (10.1.4.1 COP watchdog during STOP mode)
>>
endobj
3148 0 obj
<< /Parent 3146 0 R /Dest
[ 739 0 R /XYZ null 735 null
] /Prev 3147 0 R /Title (10.1.4.2 COP watchdog during WAIT mode)
>>
endobj
3149 0 obj
<< /Prev 3150 0 R /Dest
[ 733 0 R /XYZ null 840 null
] /Title (10.1.3 RESET pin) /Next 3146 0 R /Parent 2982 0 R
>>
endobj
3150 0 obj
<< /Prev 3144 0 R /Dest
[ 729 0 R /XYZ null 609 null
] /Title (10.1.2 Miscellaneous register) /Next 3149 0 R /Parent 2982 0 R
>>
endobj
3151 0 obj
<< /Parent 2980 0 R /Dest
[ 793 0 R /XYZ null 603 null
] /Next 3167 0 R /Title (11.3.1 Inherent)
>>
endobj
3152 0 obj
<< /Parent 2980 0 R /Dest
[ 795 0 R /XYZ null 558 null
] /Prev 3160 0 R /Title (11.3.10 Bit test and branch)
>>
endobj
3153 0 obj
<< /First 3154 0 R /Prev 2979 0 R /Dest
[ 777 0 R /XYZ null 546 null
] /Title (11.2 Instruction set) /Next 2980 0 R /Parent 2978 0 R /Last 3155 0 R /Count -6
>>
endobj
3154 0 obj
<< /Parent 3153 0 R /Dest
[ 779 0 R /XYZ null 840 null
] /Next 3159 0 R /Title (11.2.1 Register/memory Instructions)
>>
endobj
3155 0 obj
<< /Parent 3153 0 R /Dest
[ 779 0 R /XYZ null 359 null
] /Prev 3156 0 R /Title (11.2.6 Tables)
>>
endobj
3156 0 obj
<< /Prev 3157 0 R /Dest
[ 779 0 R /XYZ null 432 null
] /Title (11.2.5 Control instructions) /Next 3155 0 R /Parent 3153 0 R
>>
endobj
3157 0 obj
<< /Prev 3158 0 R /Dest
[ 779 0 R /XYZ null 531 null
] /Title (11.2.4 Read/modify/write instructions) /Next 3156 0 R /Parent 3153 0 R
>>
endobj
3158 0 obj
<< /Prev 3159 0 R /Dest
[ 779 0 R /XYZ null 666 null
] /Title (11.2.3 Bit manipulation instructions) /Next 3157 0 R /Parent 3153 0 R
>>
endobj
3159 0 obj
<< /Prev 3154 0 R /Dest
[ 779 0 R /XYZ null 741 null
] /Title (11.2.2 Branch instructions) /Next 3158 0 R /Parent 3153 0 R
>>
endobj
3160 0 obj
<< /Prev 3161 0 R /Dest
[ 795 0 R /XYZ null 687 null
] /Title (11.3.9 Bit set/clear) /Next 3152 0 R /Parent 2980 0 R
>>
endobj
3161 0 obj
<< /Prev 3162 0 R /Dest
[ 795 0 R /XYZ null 840 null
] /Title (11.3.8 Relative) /Next 3160 0 R /Parent 2980 0 R
>>
endobj
3162 0 obj
<< /Prev 3163 0 R /Dest
[ 794 0 R /XYZ null 429 null
] /Title (11.3.7 Indexed, 16-bit offset) /Next 3161 0 R /Parent 2980 0 R
>>
endobj
3163 0 obj
<< /Prev 3164 0 R /Dest
[ 794 0 R /XYZ null 570 null
] /Title (11.3.6 Indexed, 8-bit offset) /Next 3162 0 R /Parent 2980 0 R
>>
endobj
3164 0 obj
<< /Prev 3165 0 R /Dest
[ 794 0 R /XYZ null 699 null
] /Title (11.3.5 Indexed, no offset) /Next 3163 0 R /Parent 2980 0 R
>>
endobj
3165 0 obj
<< /Prev 3166 0 R /Dest
[ 794 0 R /XYZ null 840 null
] /Title (11.3.4 Extended) /Next 3164 0 R /Parent 2980 0 R
>>
endobj
3166 0 obj
<< /Prev 3167 0 R /Dest
[ 793 0 R /XYZ null 399 null
] /Title (11.3.3 Direct) /Next 3165 0 R /Parent 2980 0 R
>>
endobj
3167 0 obj
<< /Prev 3151 0 R /Dest
[ 793 0 R /XYZ null 504 null
] /Title (11.3.2 Immediate) /Next 3166 0 R /Parent 2980 0 R
>>
endobj
3168 0 obj
<< /Parent 2979 0 R /Dest
[ 773 0 R /XYZ null 369 null
] /Next 3172 0 R /Title (11.1.1 Accumulator \(A\))
>>
endobj
3169 0 obj
<< /Parent 2979 0 R /Dest
[ 776 0 R /XYZ null 382 null
] /Prev 3170 0 R /Title (11.1.5 Condition code register \(CCR\))
>>
endobj
3170 0 obj
<< /Prev 3171 0 R /Dest
[ 776 0 R /XYZ null 547 null
] /Title (11.1.4 Stack pointer \(SP\)) /Next 3169 0 R /Parent 2979 0 R
>>
endobj
3171 0 obj
<< /Prev 3172 0 R /Dest
[ 776 0 R /XYZ null 646 null
] /Title (11.1.3 Program counter \(PC\)) /Next 3170 0 R /Parent 2979 0 R
>>
endobj
3172 0 obj
<< /Prev 3168 0 R /Dest
[ 776 0 R /XYZ null 721 null
] /Title (11.1.2 Index register \(X\)) /Next 3171 0 R /Parent 2979 0 R
>>
endobj
3173 0 obj
<< /Prev 3174 0 R /Dest
[ 814 0 R /XYZ null 840 null
] /Title (12.5 MCAN bus interface DC electrical characterist...) /Next 2977 0 R /Parent 2975 0 R
>>
endobj
3174 0 obj
<< /Prev 3175 0 R /Dest
[ 808 0 R /XYZ null 840 null
] /Title (12.4 Control timing) /Next 3173 0 R /Parent 2975 0 R
>>
endobj
3175 0 obj
<< /Prev 3176 0 R /Dest
[ 806 0 R /XYZ null 840 null
] /Title (12.3 A/D converter characteristics) /Next 3174 0 R /Parent 2975 0 R
>>
endobj
3176 0 obj
<< /Prev 2976 0 R /Dest
[ 798 0 R /XYZ null 840 null
] /Title (12.2 DC electrical characteristics) /Next 3175 0 R /Parent 2975 0 R
>>
endobj
3177 0 obj
<< /Prev 2970 0 R /Dest
[ 823 0 R /XYZ null 625 null
] /Title (14.2 Verification media) /Next 2971 0 R /Parent 2969 0 R
>>
endobj
3178 0 obj
<< /Prev 3179 0 R /Dest
[ 850 0 R /XYZ null 720 null
] /Title (A.3.5 MCAN bus interface DC electrical characteris...) /Next 2968 0 R /Parent 2966 0 R
>>
endobj
3179 0 obj
<< /First 3180 0 R /Prev 3182 0 R /Dest
[ 833 0 R /XYZ null 840 null
] /Title (A.3 Electrical specifications) /Next 3178 0 R /Parent 2966 0 R /Last 3181 0 R /Count -4
>>
endobj
3180 0 obj
<< /Parent 3179 0 R /Dest
[ 833 0 R /XYZ null 765 null
] /Next 3184 0 R /Title (A.3.1 Maximum ratings)
>>
endobj
3181 0 obj
<< /Parent 3179 0 R /Dest
[ 844 0 R /XYZ null 840 null
] /Prev 3183 0 R /Title (A.3.4 Control timing)
>>
endobj
3182 0 obj
<< /Prev 2967 0 R /Dest
[ 827 0 R /XYZ null 798 null
] /Title (A.2 Memory map, register outline and block diagram...) /Next 3179 0 R /Parent 2966 0 R
>>
endobj
3183 0 obj
<< /Prev 3184 0 R /Dest
[ 842 0 R /XYZ null 840 null
] /Title (A.3.3 A/D converter characteristics) /Next 3181 0 R /Parent 3179 0 R
>>
endobj
3184 0 obj
<< /Prev 3180 0 R /Dest
[ 834 0 R /XYZ null 840 null
] /Title (A.3.2 DC electrical characteristics) /Next 3183 0 R /Parent 3179 0 R
>>
endobj
3185 0 obj
<< /Parent 2965 0 R /Dest
[ 898 0 R /XYZ null 801 null
] /Next 3205 0 R /Title (B.9.1 Maximum ratings)
>>
endobj
3186 0 obj
<< /Parent 2965 0 R /Dest
[ 916 0 R /XYZ null 503 null
] /Prev 3201 0 R /Title (B.9.7 MCAN bus interface control timing characteri...)
>>
endobj
3187 0 obj
<< /First 3188 0 R /Prev 3190 0 R /Dest
[ 877 0 R /XYZ null 840 null
] /Title (B.8 Bootstrap mode) /Next 2965 0 R /Parent 2963 0 R /Last 3189 0 R /Count -3
>>
endobj
3188 0 obj
<< /Parent 3187 0 R /Dest
[ 882 0 R /XYZ null 840 null
] /Next 3200 0 R /Title (B.8.1 Erased EPROM verification and EEPROM erasure...)
>>
endobj
3189 0 obj
<< /First 3199 0 R /Prev 3200 0 R /Dest
[ 892 0 R /XYZ null 840 null
] /Title (B.8.3 Serial RAM loader) /Parent 3187 0 R /Last 3199 0 R /Count -1
>>
endobj
3190 0 obj
<< /Prev 3191 0 R /Dest
[ 874 0 R /XYZ null 840 null
] /Title (B.7 Mask option register \(MOR\)) /Next 3187 0 R /Parent 2963 0 R
>>
endobj
3191 0 obj
<< /Prev 3192 0 R /Dest
[ 873 0 R /XYZ null 840 null
] /Title (B.6 EEPROM options register \(OPTR\)) /Next 3190 0 R /Parent 2963 0 R
>>
endobj
3192 0 obj
<< /First 3193 0 R /Prev 3195 0 R /Dest
[ 864 0 R /XYZ null 840 null
] /Title (B.5 EPROM) /Next 3191 0 R /Parent 2963 0 R /Last 3194 0 R /Count -3
>>
endobj
3193 0 obj
<< /Parent 3192 0 R /Dest
[ 864 0 R /XYZ null 579 null
] /Next 3198 0 R /Title (B.5.1 EPROM read operation)
>>
endobj
3194 0 obj
<< /Parent 3192 0 R /Dest
[ 866 0 R /XYZ null 627 null
] /Prev 3198 0 R /Title (B.5.3 EPROM/EEPROM/ECLK control register)
>>
endobj
3195 0 obj
<< /Prev 3196 0 R /Dest
[ 860 0 R /XYZ null 840 null
] /Title (B.4 Block diagram, memory map and register outline...) /Next 3192 0 R /Parent 2963 0 R
>>
endobj
3196 0 obj
<< /Prev 3197 0 R /Dest
[ 856 0 R /XYZ null 528 null
] /Title (B.3 CANE) /Next 3195 0 R /Parent 2963 0 R
>>
endobj
3197 0 obj
<< /Prev 2964 0 R /Dest
[ 856 0 R /XYZ null 615 null
] /Title (B.2 VPP6) /Next 3196 0 R /Parent 2963 0 R
>>
endobj
3198 0 obj
<< /Prev 3193 0 R /Dest
[ 866 0 R /XYZ null 840 null
] /Title (B.5.2 EPROM program operation) /Next 3194 0 R /Parent 3192 0 R
>>
endobj
3199 0 obj
<< /Parent 3189 0 R /Dest
[ 892 0 R /XYZ null 450 null
] /Title (B.8.3.1 Jump to start of RAM \($0051\))
>>
endobj
3200 0 obj
<< /Prev 3188 0 R /Dest
[ 882 0 R /XYZ null 675 null
] /Title (B.8.2 EPROM/EEPROM parallel bootstrap) /Next 3189 0 R /Parent 3187 0 R
>>
endobj
3201 0 obj
<< /Prev 3202 0 R /Dest
[ 916 0 R /XYZ null 840 null
] /Title (B.9.6 MCAN bus interface DC electrical characteris...) /Next 3186 0 R /Parent 2965 0 R
>>
endobj
3202 0 obj
<< /Prev 3203 0 R /Dest
[ 914 0 R /XYZ null 840 null
] /Title (B.9.5 A/D converter characteristics) /Next 3201 0 R /Parent 2965 0 R
>>
endobj
3203 0 obj
<< /Prev 3204 0 R /Dest
[ 908 0 R /XYZ null 840 null
] /Title (B.9.4 Control timing) /Next 3202 0 R /Parent 2965 0 R
>>
endobj
3204 0 obj
<< /Prev 3205 0 R /Dest
[ 907 0 R /XYZ null 840 null
] /Title (B.9.3 EPROM electrical characteristics) /Next 3203 0 R /Parent 2965 0 R
>>
endobj
3205 0 obj
<< /Prev 3185 0 R /Dest
[ 899 0 R /XYZ null 840 null
] /Title (B.9.2 DC electrical characteristics) /Next 3204 0 R /Parent 2965 0 R
>>
endobj
3206 0 obj
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3207 0 obj
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3208 0 obj
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